Where performance meets integration.

As demand grows for smaller, thinner, and more powerful devices, advanced wafer-level designs have become essential. Wafer Level Packaging (WLP) enables high performance and multi-functionality while maintaining tight form-factor and cost targets—addressing the manufacturing and integration challenges of today’s consumer, communications, and industrial electronics.

Inside the Technology

Package Level Integration

Wafer level packaging formats including Fan-in WLP (FIWLP) and Fan-out WLP (FOWLP)
Embedded component and interconnect technologies such as Integrated Passive Devices (IPD) and Through-Silicon Via (TSV)
Specialized package solutions including Encapsulated Chip Package (ECP) and RFID packaging
Enablement of full turnkey advanced flip chip and wafer-level packaging solutions

Inside the Technology

Broad experience across wafer bump alloys and processes, including printed bump, ball drop, and plated approaches
Support for eutectic, lead-free, and copper pillar bump alloys
Wafer bumping and redistribution services for 200 mm and 300 mm wafer sizes
Enablement of full turnkey advanced flip chip and wafer-level packaging solutions

Inside the Technology

Broad experience across wafer bump alloys and processes, including printed bump, ball drop, and plated approaches
Support for eutectic, lead-free, and copper pillar bump alloys
Wafer bumping and redistribution services for 200 mm and 300 mm wafer sizes
Enablement of full turnkey advanced flip chip and wafer-level packaging solutions

Technical Highlights

Package Level Integration

High-performance fan-out WLP (eWLB and ECP) delivering strong bandwidth, performance, size, and cost advantages
Millimeter-wave-optimized wafer-level AiP antenna solutions supporting improved high-frequency performance, shorter interconnects, lower conductor loss, and optimized dielectric properties
Five-sided protection via FI-ECP and eWLCSP wafer-level technologies

Package Level Integration

eWLB platform enables smaller footprints and higher I/O density for more efficient package designs
2D/2.5D/3D WLP integration—using side-by-side or stacked chips, embedded devices, and dual-sided RDL—to enable complex PoP and SiP solutions
BGBM packaging—wafer-thinning plus backside metallization—to enhance thermal diffusion, electrical performance, and reduce impedance for MOSFETs, IGBTs, and other vertical-structure devices