About
About
Culture & Values
Leadership Team
Worldwide Locations
Ethics & Compliance
Careers
Applications
Applications
Automotive
Computing
Memory
AI Edge
Power & Energy
Technology & Services
Technology & Services
Turnkey Services
Test Services
Design Services
Packaging Services
2.5/3D Integration
Wafer Level
System-in-Package
Flip Chip Packaging Technology
Superior Memory Packaging
Wafer Bumping
Wirebond Packaging
Technology & Solutions
Technology & Services
Turnkey Services
Test Services
Design Services
Packaging Services
Semiconductor Package Integration Design
Wafer Probing
Wafer Bumping
Assembly
Global Drop Shipping
Technology
Advanced 2.5D / 3D Packaging Solutions
Ultra High-Density Advanced SiP Technology
Ultra-Thin Wafer Level Packaging Technology
High-Performance Flip Chip Technology
Superior Memory Packaging Technology
Sustainability
Sustainability
Green Manufacturing
Conflict-Free Mineral Policy
ESG
ESG
ESG
Green Manufacturing
Responsible Sourcing
Newsroom
Contact Us
2.5/3D Packaging
Higher density, better performance, and more efficient integration.
Architecture beyond the planar.
Advanced 2.5D and 3D packaging stacks and interconnects multiple components to maximize functionality and performance.
Inside the Technology
Package Level Integration
Stacked Die (SD)
enables compact multi-die designs.
Package-on-Package (PoP)
stacks memory and logic packages.
Package-in-Package (PiP)
integrates packaged and bare chips into FBGAs.
Enablement of full turnkey
advanced flip chip and wafer-level packaging solutions
Wafer Level Integration
3D wafer level packaging (WLP)
with redistribution layers.
eWLB supports high-density connections
in 2D, 2.5D, and 3D.
eWLCSP™ enhances CSP reliability
, while WLCSP improves density.
Enablement of full turnkey
advanced flip chip and wafer-level packaging solutions
Silicon Level Integration
3D IC design
eliminates interposers and substrates.
2.5D eWLB
enables dense interconnects without TSVs.
2.5D MEOL
uses TSVs for cost-effective, high-volume integration
Enablement of full turnkey
advanced flip chip and wafer-level packaging solutions
Technical Highlights
Package Level Integration
Stacked Die (SD) enables compact multi-die designs.
Package-on-Package (PoP)
stacks memory and logic packages.
Package-in-Package (PiP)
integrates packaged and bare chips into FBGAs.
Package Level Integration
3D wafer level packaging (WLP)
with redistribution layers.
eWLB
supports high-density connections in 2D, 2.5D, and 3D.
eWLCSP™
enhances CSP reliability, while WLCSP improves density.
Applications
Mobile Devices
Data Centers
Automotive Electronics
Automotive Electronics
Automotive Electronics
Download Documents
Lorem Ipsum Dolor Sit Amet
Lorem Ipsum Dolor Sit Amet
Lorem Ipsum Dolor Sit Amet
Lorem Ipsum Dolor Sit Amet
Lorem Ipsum Dolor Sit Amet
Lorem Ipsum Dolor Sit Amet
Explore All Technologies
2.5D / 3D Integration
Integrate multiple components into a single compact package.
System-in-Package (SiP)
Integrate multiple components into a single compact package.
Wafer Level Packaging
Integrate multiple components into a single compact package.
High-Performance Flip Chip Technology
Integrate multiple components into a single compact package.
Superior Memory Packaging Technology
Integrate multiple components into a single compact package.
Wirebond Packaging
Integrate multiple components into a single compact package.
Wafer Bumping
Integrate multiple components into a single compact package.
